Safety Integrity Level (SIL)

Rizzo Engineering’s team of consultants can lead and facilitate SIL Allocation studies or provide SIL Verification Studies.

SIL Allocation Studies

Safety Integrity Level Allocation studies, ranging from calibrated Risk Graphs, to semi-quantitative Layers of Protection Analysis (LOPA) and fully-quantitative Fault Tree Analysis (FTA).

A SIL Determination study is required to determine the Safety Integrity Level requirements, SIL requirements, for Safety Instrumented Functions (SIFs). This involves determining the necessary risk reduction required to meet the tolerable risk for specific hazardous scenarios. This typically involves:

• Determining the potential frequency and consequence of a specific hazard;
• Determining the risk reduction provided by other measures and the resulting risk gap;
• Assignment of SIL requirements for SIFs based on any resulting risk gaps in accordance with IEC and EN norms.

As well as the use of a LOPA as part of a SIL Allocation study, other methods such as a calibrated risk graph or FTA can also be used to identify the risk gap and determine the SIL requirements for the SIF under consideration. These methods can be analysed quantitatively or semi-quantitatively based on the outputs from the HAZOP / PHA study.

As part of the SIL Allocation study, Rizzo Engineering can provide:

• A SIL Allocation workshop facilitated by one of Rizzo Engineering’s experienced SIL Allocation consultants;
• Calibration of client specific risk criteria;
• Demonstration of the As Low as Reasonably Practical (ALARP) principle using Cost Benefit Analysis (CBA) where appropriate;
• A record of the SIL Allocation study through the production of a subsequent report, providing an overview of the target SIL for the specified SIF under study as well as detailing the study as a whole.

Following on from a SIL Allocation study, Rizzo Engineering can conduct a SIL Verification assessment to verify if the SIFs meets the specified targets, as per the requirements of IEC / EN. Norms.

SIL Verification Studies

SIL Verification studies, assessing the SIL capability of specified Safety Instrumented Functions (SIFs) using methods such as:

• Fault Tree Analysis (FTA);
• Reliability Block Diagrams (RBDs) or;
• Failure Modes Effects and Criticality Analysis (FMECA).

A SIL Verification assessment is typically carried out following a SIL Allocation study, to verify that the SIFs, which have been (typically) identified as part of a Layers of Protection Analysis (LOPA), meet their targeted SIL level.

Rizzo Engineering has extensive experience of carrying out SIL Verification studies to address random hardware failures and minimum architecture in terms of hardware fault tolerance (HFT) for the SIFs under consideration as per the requirements specified in IEC and EN Norms.

Our SIL Verification consultants can also provide plant reliability, availability and maintainability (RAMS) studies using similar techniques.

Rizzo Engineering can provide:

• An assessment of the random hardware reliability, and minimum architecture in terms of Hardware Fault Tolerance (HFT) of each SIF, comprising input devices, logic modules, actuator and final element devices;
• SIL Verification assessments of proposed or existing SIFs conducted using failure rate data provided by the client / vendor, or from Rizzo Engineering’s failure rate database. This can be used to confirm, or otherwise, hardware reliability and compliance with safety requirements parameters such as Probability of Failure on Demand (PFD) and frequency of a dangerous failure (PFH);
• Sensitivity analyses to optimise proof test and automatic test intervals;
• Recommendations for SIF modifications where the SIL Verification assessment has shown that the SIL target cannot be met, detailing the improvement options that will allow the target to be met;

Documentation of the assessment process, providing a visible and traceable analysis in a formal report.